1. Field of the Invention
The present invention relates to a four quadrant multiplier circuit which has particular, but not exclusive, application in demodulating FM signals in zero-IF receivers.
2. Description of the Related Art
The use of four quadrant multiplier circuits for demodutating FM signals is known, for example, from British Patent Specification 1 530 602 in which baseband I and Q signals are multiplied by the differentials of the Q and I signals, respectively. These multipliers need a high dynamic range because, unless the demodulator is preceded by an automatic gain control (agc) system with infinitely good regulation, their signal inputs will not be constant. Dynamic range in the present specification means the range of signal inputs over which adequate demodulator performance is obtained, given that statistical DC offset causes distortion at low signal input levels and limiting non-linearity causes distortion at high signal input levels. Noise is generally not a significant constraint at this late stage in a receiver. Basic four quadrant multiplier circuits are already known, for example, from U.S. Pat. No. 3,241,078. This citation discloses a circuit comprising a first long-tailed pair circuit for receiving a first pair of balanced voltage inputs and a second long-tailed pair circuit comprising a second pair of long-tailed pair circuits for processing signals at a second pair of balanced voltage inputs. There are two main drawbacks to this circuit. The dynamic range is barely sufficient for this application and the inputs are stacked one above the other across the supply. This stacking means that the inputs lie in two non-overlapping voltage ranges and makes it difficult to operate at low supply voltages.
Four quadrant multiplier circuits without stacking are already known, for example, from Chadwick, P. E. "Low power, low voltage receiver integrated circuits", Institution of Electronic and Radio Engineers Publication Number 78, Proceedings of the Fourth International Conference on Land Mobile Radio, University of Warwick, Coventry 15th-17th Dec. 1987, pages 155-161. The cited circuit uses PNP transistors in the first tailed pair circuit. Stacking is obviated in that the signal path between the first and the second pair of long-tailed pair circuits is by way of current mirror circuits but the problem of limited dynamic range remains. A drawback to this circuit is that the PNP transistors are a source of difficulty because lateral PNP transistors available in standard bipolar processes are slow and have a very low gain. Although the slowness can be tolerated in some applications, the very low gain lowers the input resistance of the input port for the second pair of balance inputs and makes it difficult to maintain consistent performance at large signal input levels. Processes are known for producing vertical PNP transistors but these add to the cost of the integrated circuit.